JEDEC JESD8-6 PDF

JEDEC JESD8-6 PDF

$36.00

ADDENDUM No. 6 to JESD8 – HIGH SPEED TRANSCEIVER LOGIC (HSTL)- A 1.5 V OUTPUT BUFFER SUPPLY VOLTAGE BASED INTERFACE STANDARD FOR DIGITAL INTEGRATED CIRCUITS

Published by Publication Date Number of Pages
JEDEC 08/01/1995 20
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Description

JEDEC JESD8-6 – ADDENDUM No. 6 to JESD8 – HIGH SPEED TRANSCEIVER LOGIC (HSTL)- A 1.5 V OUTPUT BUFFER SUPPLY VOLTAGE BASED INTERFACE STANDARD FOR DIGITAL INTEGRATED CIRCUITS

This standard is a 1.5 volt high performance CMOS-based interface document suitable for high I/O count CMOS and BiCMOS devices operating at frequencies in excess of 200 Mhz.

Product Details

Published:
08/01/1995
Number of Pages:
20
File Size:
1 file , 410 KB
Note:
This product is unavailable in Russia, Ukraine, Belarus

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