JEDEC JESD52 PDF

Description

JEDEC JESD52 – STANDARD FOR DESCRIPTION OF LOW VOLTAGE TTL-COMPATIBLE CMOS LOGIC DEVICES

This standard describes dc interface specifications and test environment for these devices that operate with 2.7 V to 3.6 V power supplies. The goal is to provide a consistent set of dc specifications for reference by logic suppliers and users alike.

Product Details

Published:

11/01/1995

Number of Pages:

15

File Size:

1 file , 240 KB

Note:

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