JEDEC JESD 82-29A PDF

JEDEC JESD 82-29A PDF

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DEFINITION OF THE SSTE32882 REGISTERING CLOCK DRIVER WITH PARITY AND QUAD CHIP SELECTS FOR DDR3/DDR3L/DDR3U RDIMM 1.5 V/1.35 V/1.25 V APPLICATIONS

Published by Publication Date Number of Pages
JEDEC 12/01/2010 80
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Description

JEDEC JESD 82-29A – DEFINITION OF THE SSTE32882 REGISTERING CLOCK DRIVER WITH PARITY AND QUAD CHIP SELECTS FOR DDR3/DDR3L/DDR3U RDIMM 1.5 V/1.35 V/1.25 V APPLICATIONS

This standard defines standard specifications of DC interface parameters, switching parameters, and test loading for definition of the SSTE32882 registered buffer with parity for driving address and control nets on DDR3/DDR3L/DDR3U RDIMM applications. The purpose is to provide a standard for the SSTE32882 logic device, for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use.

Product Details

Published:
12/01/2010
Number of Pages:
80
File Size:
1 file , 640 KB
Note:
This product is unavailable in Russia, Ukraine, Belarus

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