JEDEC JESD 8-9B PDF

JEDEC JESD 8-9B PDF

$43.00

ADDENDUM No. 9B to JESD8 – STUB SERIES TERMINATED LOGIC FOR 2.5 VOLTS (SSTL_2): Includes Errata and Corrected Page 7 as of October 18, 2002

Published by Publication Date Number of Pages
JEDEC 05/01/2002 28
PDF FormatPDF FormatMulti-User-AccessMulti-User AccessPrintablePrintableOnline downloadOnline Download
Category:

Description

JEDEC JESD 8-9B – ADDENDUM No. 9B to JESD8 – STUB SERIES TERMINATED LOGIC FOR 2.5 VOLTS (SSTL_2): Includes Errata and Corrected Page 7 as of October 18, 2002

This standard defines the input, output specifications and ac test conditions for devices that are designed to operate in the SSTL_2 logic switching range, nominally 0 V to 2.5 V. The standard may be applied to ICs operating with separate VDD and VDDQ supply voltages. This standard has been developed particularly with the objective of providing a relatively simple upgrade path from MOS push-pull interface designs. The standard is particularly intended to improve operation in situations where busses must be isolated from relatively large stubs.

Product Details

Published:
05/01/2002
Number of Pages:
28
File Size:
1 file , 180 KB
Note:
This product is unavailable in Russia, Ukraine, Belarus

In Demand Now