JEDEC JESD 47G.01 PDF
$40.00
STRESS-TEST-DRIVEN QUALIFICATION OF INTEGRATED CIRCUITS
standard by JEDEC Solid State Technology Association, 04/01/2010
Description
This standard describes a baseline set of acceptance tests for use in qualifying electronic components as new products, a product family, or as products in a process which is being changed.
Product Details
- Published:
- 04/01/2010
- Number of Pages:
- 26
- File Size:
- 1 file , 240 KB
- Note:
- This product is unavailable in Russia, Ukraine, Belarus