IEC 61691-3-3 Ed. 1.0 en – Behavioural languages – Part 3-3: Synthesis in VHDL
This standard supports the synthesis and verification of hardware designs, by defining vector types for representing signed or unsigned integer values and providing standard interpretations of widely used scalar VHDL values. Includes package bodies, as described in annex A, which are available in electronic format either on a diskette affixed to the back cover, or as a downloadable file from the IEC Web Store.
Product Details
Edition:
1.0
Published:
06/28/2001
Number of Pages:
48
File Size:
1 file , 290 KB
Note:
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