Name: ESD TR17.0-01 PDF - Engineering Standards Download
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ESD TR17.0-01 – Methodologies in Electronic Production Lines – Best Practices Used in Industry

For more than two decades, the robustness of integrated circuits (ICs) against electrostatic discharges (ESD) has been defined by two values, 2,000 volts human body model (HBM) robustness and 500 volts charged device model (CDM) robustness. It has been assumed that both of these robustness levels would provide a safe margin for handling of ICs during processing, assembly, and testing. Both values are “historic” values and have been commonlyaccepted, with some exceptions towards higher values for specific applications.

Rapid technology scaling and increasing demands for high-speed interfaces with very low pin capacitance are making it challenging to achieve the historic ESD target levels. It is not clear whether the historic target levels are justified by ?real? ESD threats in electronic production and testing facilities. Depending on the ESD control, the target levels could be too high, resulting in over-engineering or performance constraints and, consequently, adding additional costs. It could be argued that with well-implemented static control process according to international standards such as ANSI/ESD S20.20 [1] or IEC 61340-5-1 [2], a HBM robustness of 2,000 volts exceedsthe maximum possible charging of personnel by more than one order of magnitude and, therefore, the HBM robustness could be reduced. Additionally, in many cases during processing, assembly and testing, charging of devices could not be avoided and in many processes 500 volts charging can be exceeded easily – questioning whether a CDM robustness of 500 volts will really guarantee safe handling.

Considering today’s commonly practiced ESD control measures and the ESD design constraints, the Industry Council on ESD Targets suggests a reduction of the HBM robustness target from 2,000 volts to 1,000 volts [3] and a reduction of the CDM robustness target from 500 volts to 250 volts [4]. It is clear that future technology nodes and high-speed applications will demand further reduction of HBM and CDM robustness.

With decreasing ESD robustness of ICs, ESD control measures during handling of ICs are becoming increasingly important and detailed process assessments will be required. In many process steps, the basic principles of ESD control measures can be assessed easily. For example, the process steps in which devices are handled manually require grounded personnel; the grounding can be verified by ESD testers combined with an access control. However, in automated tools the assessment of charging and possible discharge paths can be a difficult task.