JEDEC JESD 35-A PDF

Description

JEDEC JESD 35-A – PROCEDURE FOR WAFER-LEVEL-TESTING OF THIN DIELECTRICS

The revised JESD35 is intended for use in the MOS Integrated Circuit manufacturing industry. It describes procedures developed for estimating the overall integrity and reliability of thin gate oxides. Three basic test procedures are described, the Voltage-Ramp (V-Ramp), the Current-Ramp (J-Ramp) and the new Constant Current (Bounded J-Ramp) test. Each test is designed for simplicity, speed and ease of use. The standard has been updated to include breakdown criteria that are more robust in detecting breakdown in thinner gate oxides that may not experience hard thermal breakdown.

Product Details

Published:

03/01/2010

Number of Pages:

47

File Size:

1 file , 680 KB

Note:

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