JEDEC JESD 78B PDF
$43.00
IC LATCH-UP TEST
standard by JEDEC Solid State Technology Association, 12/01/2008
Description
This standard has been adopted by the Defense Logistics Agency (DLA) as project 5962-1880. This standard establishes a defined method for latch-up testing of ICs. It defines Classes and Levels for a device’s latch-up capability so that both the user and supplier understand a device’s latch-up capabilities. It is applicable to NMOS, CMOS, Bipolar, and all variations and combinations of these technologies. Latch-up is an extremely important factor in determining product reliability. This document contains the corrected figure 4 to include T6 on page 12, this change was made in January 1998.
Product Details
- Published:
- 12/01/2008
- Number of Pages:
- 27
- File Size:
- 1 file , 250 KB
- Note:
- This product is unavailable in Russia, Ukraine, Belarus