JEDEC JESD 78C PDF
$43.00
IC LATCH-UP TEST
standard by JEDEC Solid State Technology Association, 09/01/2010
Description
This standard has been adopted by the Defense Logistics Agency (DLA) as project 5962-1880. This specification covers the I-test and the overvoltage latch-up testing of integrated circuits. The purpose of this specification is to establish a method for determining IC latch-up characteristics and to define latch-up failure criteria. Latch-up characteristics are extremely important in determining product reliability and minimizing No Trouble Found (NTF) and Electrical Overstress (EOS) failures due to latch-up. This test method is applicable to NMOS, CMOS, bipolar, and all variations and combinations of these technologies.
Product Details
- Published:
- 09/01/2010
- Number of Pages:
- 28
- File Size:
- 1 file , 190 KB
- Note:
- This product is unavailable in Russia, Ukraine, Belarus