SystemVerilog – Part 2: Universal Verification Methodology Language Reference Manual

Published by	Publication Date	Number of Pages
IEC	07/01/2021	478

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Category: IEC

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IEC 62530-2 Ed. 1.0 en – SystemVerilog – Part 2: Universal Verification Methodology Language Reference Manual

The Universal Verification Methodology (UVM) that can improve interoperability, reduce the cost of using intellectual property (IP) for new projects or electronic design automation (EDA) tools, and make it easier to reuse verification components is provided. Overall, using this standard will lower verification costs and improve design quality throughout the industry. The primary audiences for this standard are the implementors of the UVM base class library, the implementors of tools supporting the UVM base class library, and the users of the UVM base class library.